The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. In addition, many of the individual devices within the wafer are being manufactured with smaller physical dimensions. As the number of electronic devices per given area of the silicon wafer increases, and as the size of the individual devices decreases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS), complementary MOS (CMOS), bipolar complementary MOS (BiCMOS), and bipolar transistors.
The manufacture of such semiconductor devices often includes the creation of structure within the device including metal layers and individual devices having small physical dimensions. The metal layers and individual devices must be arranged according to the device specifications, which often require etching in order to create the desired shapes, patterns, or connections.
For instance, it is sometimes necessary to create electrical connections between metal layers within the device. Typically, a dielectric material is located between metal layers and acts as an insulator. Via etch is a process that may be used to open holes through the dielectric in order to allow the creation of a connection between the conductive layers. Once a hole is created, material is placed in the hole, creating the connection between layers of metal within the device. In addition, it is also sometimes necessary to create contacts for regions in the device, such as gate, source, drain, or field isolation regions. Contact etching may be used to open contact holes to the devices. Once a hole is created, material is placed in the contact hole, creating a contact connection to the device.
When creating holes in the dielectric for making an electrical connection, it is often important that the etching pass through all of the dielectric material and expose the underlying conductive layer and stop precisely at the desired point. A method for etching the dielectric without etching the metal is selective etching. Selective etching is a process by which an etchant is used that etches only the dielectric, leaving the metal relatively intact. When a non-selective etching process is used, accurate determination of the endpoint is necessary to prevent over-etching and also under-etching.
Wet etching is a low-cost, reliable, high throughput process that has been used in semiconductor fabrication. Wet etching may also be selective, making detection of the endpoint of the etching process less necessary. However, wet etching is limited in that it does not adequately perform the etching process when the features needed to be defined, such as the size of a hole needing to be etched, is less than about 3 microns wide. This limitation is due to the fact that wet etching is an isotropic process, which results in undercutting of the dielectric during the etching process when the thickness of the film being etched is comparable to the width of the pattern being etched. Since many films used in semiconductor device fabrication are in a range of less than 3 microns, creating patterns in a range of less than 3 microns becomes difficult. Therefore, wet-etching is not suitable for use in the formation of via holes or contact holes wherein the width of such holes is less than 3 microns, and particularly not suitable when the width of such holes is less than 0.25 microns.
Dry etching is an alternative to wet etching that can be used for etching in the sub-3 micron range, since it offers the capability of anisotropic etching. Dry etching includes processes such as physical sputtering, ion beam milling, reactive ion etching (RIE), and plasma etching. Although dry etching may be performed anisotropically, it does not exhibit the high selectivity to substrate and mask material that is available with wet etching systems.
Detecting the endpoint of the dry etch process for sub-0.25 micrometer contact and via etch processes is a challenge. For sub-micron technologies, at contact and via layers, the typical exposed area may be less than 2% of the total wafer area. In some cases, the exposed area could be less than 1%. This small area may render optical detection of etch end point impossible due to a weak signal. Timed etch contact and via etch processes are used instead of optical detection. However, with timed etch processes, good via and contact etch process control becomes difficult due to the over-etching and under-etching issues discussed above. Dielectric film thicknesses, film composition, dielectric etch rate, uniformity, selectivity to the under-layer, etc., all have a major impact on the contact and via etch process control, possibly leading to device failure and reliability problems. Therefore, endpoint detection capability is important for developing a manufacturable sub-micron contact or via etch processes.